RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81000: Master Interrupt Register (MSTR_INTR_REG)
Bit
Type
Function
Default
15
14
13
12
11
10
9
RO
RO
Unused
Unused
X
X
X
X
X
0
RO
Unused
RO
Unused
RO
Unused
R2C
R2C
R2C
R2C
R2C
R2C
R2C
RO
R_UTOP_RUNT_CL
UTOP_LFIFO_FULL
T_UTOP_XFR_ERR
T_UTOP_FULL
UTOP_PAR_ERR
Unused
0
8
0
7
0
6
0
5
X
0
4
RAM_PAR_ERR
Unused
3
X
X
X
0
2
RO
Unused
1
RO
Unused
0
RO
A1SP_INTR
This register is the top of the Interrupt Tree. It indicates which lower level
interrupt registers have interrupts pending. The UTOPIA Interface error bits and
RAM parity error bits are cleared on read, the other bits are current status and
will remain set as long as the underlying condition remains active.
A1SP_INTR
When set, there is an interrupt pending from the A1SP block. Read the
A1SP_INTR_REG to determine the cause of the interrupt. This bit indicates
current status and will clear only when no interrupt conditions remain in
A1SP_INTR_REG. On read:
0) No interrupt pending from the A1SP block
1) Interrupt pending from the A1SP block
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
259
PMC [ PMC-SIERRA, INC ]
