RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x80200H, 01H … 07H: Low Speed Line n Configuration
Registers(LS_Ln_CFG_REG)
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
R/W
Unused
Unused
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unused
Unused
Unused
Unused
Unused
Bit 8
Unused
Bit 7
Unused
Bit 6
Unused
Bit 5
Unused
Bit 4
Unused
Bit 3
Unused
Bit 2
Unused
Bit 1
MVIP_EN
MF_SYNC_MODE
Bit 0
R/W
This register configures how independent lines are handled by the Line Interface
Block in Direct Mode..
MF_SYNC_MODE
Controls if the line sync signal (RL_SYNC and TL_SYNC) function as frame
sync signals or multi-frame sync signals.
1) Sync signals are multi-frame sync signals
0) Sync signals are frame sync signals
MVIP_EN
When set selects the MVIP-90 format for external line data instead of the
normal format. On read:
1) This line is in MVIP-90 mode
0) This line is in normal mode
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
256
PMC [ PMC-SIERRA, INC ]
