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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
Register 0x80125: UI to UI Loopback VCI (U2U_LOOP_VCI)  
Bit  
Type  
Function  
Default  
15:0  
R/W  
U2U_LOOP_VCI  
0000H  
U2U_LOOP_VCI(15:0)  
If VCI_U2U_LOOP is set in the UI_COMN_CFG_REG, any cell received from  
the UI bus, with a VCI which matches this programmed VCI, will be sent back  
out to the UI bus. To avoid any momentary corruption of incoming cell data,  
the value of this register should only be changed only when VCI_U2U_LOOP  
in UTO_CFG_REG is disabled and UI_EN in UTO_CFG_REG s disabled.  
11.4 Line Interface Registers  
These registers control the configuration and report status for the Line Interface.  
Gaps within the address space are reserved and should not be read or written.  
The Line interface registers are broken into the following sections:  
Table 22 Line Interface Register Memory Map Summary  
Address  
Register Description  
0x802XX  
General Line Configuration Registers  
11.5 Direct Mode Registers  
These registers are selected when the address = 0x802XX.  
Table 23 Direct Low Speed Mode Register Memory Map  
Offset  
0x00 – 0x0F Low Speed Line Configuration Registers  
0x10 Line Mode Register  
Register Description  
Register Mnemonic  
LS_Ln_CFG_REG  
LINE_MODE_REG  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
255  
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