欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM73123-PI的Datasheet PDF文件第20页浏览型号PM73123-PI的Datasheet PDF文件第21页浏览型号PM73123-PI的Datasheet PDF文件第22页浏览型号PM73123-PI的Datasheet PDF文件第23页浏览型号PM73123-PI的Datasheet PDF文件第25页浏览型号PM73123-PI的Datasheet PDF文件第26页浏览型号PM73123-PI的Datasheet PDF文件第27页浏览型号PM73123-PI的Datasheet PDF文件第28页  
RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
Ram parity error  
UTOPIA parity error  
Transmit UTOPIA FIFO is full  
Transmit UTOPIA transfer error  
UTOPIA loopback FIFO is full  
UTOPIA runt cell is detected  
For the AAL1 block the following conditions can cause an interrupt,  
each of which can be masked. A 64 entry FIFO is used to track  
receive and transmit status.  
A receive queue sticky bit was just set (individual mask per  
sticky bit)  
Receive queue entered underrun state  
Receive queue exited underrun state  
DBCES bitmask changed  
Receive Status FIFO overflow  
Transmit Frame Advance FIFO full  
Reception of OAM cells  
Change in idle state of a channel enabled for idle channel  
detection  
Transmit Channel Idle State change FIFO overflow  
Line frame resync event  
Transmit ATM Layer Processor (TALP) FIFO full  
Provides a 16-bit microprocessor interface to internal registers, and  
one external 128K x 16(18) (10 ns) Pipelined Single-Cycle Deselect  
Synchronous SRAMs, or Synchronous ZBT SRAMs.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
24  
 复制成功!