RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
• Provides a transmit buffer which can be used for Operations,
Administration and Maintenance (OAM) cells as well as any other
user-generated cells such as AAL5 cells for ATM signaling. A
corresponding receive buffer exists for the reception of OAM cells or
non-AAL1 data cells.
• Includes an internal E1/T1 clock synthesizer for each line which can
generate a nominal E1/T1 clock or be controlled via Synchronous
Residual Time Stamp (SRTS) clock recovery method in Unstructured
Data Format (UDF) mode or a programmable weighted moving
average adaptive clocking algorithm. DS3 and E3 SRTS or adaptive
clocking is supported using an external clock synthesizer and the clock
control port.
• The clock synthesizers can also be controlled externally to provide
customization of SRTS or adaptive algorithms. SRTS can also be
disabled via a hardware input. Adaptive and SRTS information is
output to a port for external processing for both low speed and high
speed mode, if needed. Buffer depth is provided in units of bytes. The
synthesizer can be set to 256 discrete frequencies between either +/-
100 ppm for E1 or +/-200 ppm for T1.
• Low-power 2.5 Volt CMOS technology with 3.3 Volt, 5 Volt tolerant I/O.
• 324-pin fine pitch plastic ball grid array (PBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
25
PMC [ PMC-SIERRA, INC ]
