RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
1
FEATURES
The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor
is a monolithic single chip device that provides DS1, E1, E3, or DS3 line
interface access to an ATM Adaptation Layer One (AAL1) Constant Bit
Rate (CBR) ATM network. It arbitrates access to an external SRAM for
storage of the configuration, the user data, and the statistics. The device
provides a microprocessor interface for configuration, management, and
statistics gathering. PMC-Sierra also provides a software device driver for
the AAL1gator-8 device.
• Compliant with the ATM Forum’s Circuit Emulation Services (CES)
specification (AF-VTOA-0078), and the ITU-T I.363.1
• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES).
Compliant with the ATM Forum’s DBCES specification (AF-VTOA-
0085). Supports idle channel detection via processor intervention,
CAS signaling, or data pattern detection. Provides idle channel
indication on a per channel basis.
• Supports non-DBCES idle channel detection by activating a queue
when any of its constituent time slots are active, and deactivating a
queue when all of its constituent time slots are inactive.
• Provides AAL1 segmentation and reassembly of 8 individual E1 or T1
lines, 2 H-MVIP lines at 8 MHz, or 1 E3 or DS3 or STS-1 unstructured
line.
•
• Provides a standard UTOPIA level 2 Interface which optionally
supports parity and runs up to 52 MHz. Only Cell Level Handshaking
is supported. The following modes are supported:
• 8/16-bit Level 2, Multi-Phy Mode (MPHY)
• 8/16-bit Level 1, SPHY
• 8-bit Level 1, ATM Master
• Provides an optional 8/16-bit Any-PHY slave interface.
• Supports up to 256 Virtual Channels (VC).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
20
PMC [ PMC-SIERRA, INC ]
