RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 62 shows the memory region broken into three blocks. The first block,
A1SP SRAM, is the memory mapped registers which are mostly contained within
SRAM. The second block, Internal Registers, is composed of configuration
registers common to the entire chip that are contained internally to the chip. The
final block is the test registers.
Figure 62 Memory Map
00000
A1SP SRAM
1FFFF
80000
Internal Registers
BFFFF
C0000
FFFFF
Test Registers
Figure 63 shows the structure of the A1SP block within the external SSRAM.
The addresses listed in the figure represent the relative location within the A1SP
block. The first block, Control Registers, contains registers which are common to
both the transmit block and the receive block. The second and third blocks
contain registers which are specific to the transmit block and the receive block
respectively.
Figure 63 A1SP SRAM Memory Map
00000
Control Registers
0001F
00020
Transmit Data Structures
07FFF
08000
Receive Data Structures
1FFFF
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