PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
If using the architecture shown in Figure 108 at maximum frequency (40.00 MHz), the recom-
mended worst-case parameters for each part are listed in Table 26 on page 195. At lower speeds
these numbers can be adjusted.
/MEM_WE(0)
/MEM_WE(1)
/MEM_CS
/WE(0)
/WE(1)
/CS
(2) 128K × 8
SRAMs
/OE
A(0:16)
/MEM_OE
D(0:15)
16
MEM_DATA(0:15)
MEM_ADDR(0:16)
•
17
•
AAL1gator II
(PM73121)
/SP_DATA_EN
SP_DATA_DIR
SP_DATA_CLK
/SP_ADD_EN
16
40.00 MHz
SYS_CLK
Vcc
A(0:15)
Y(0:16)
G
Octal Bus
Transceivers and
Registers
SAB
CBA
SBA
G
Octal Buffers with
Tristate Outputs
(FCT244)*
DIR
CAB
(FCT646)*
A(0:16)
B(0:15)
Gnd
ADDRESS BUS (17)
PROC_DATA (0:15)
16
PROC_ADD (0:16)
Microprocessor
NOTES: Series terminating resistors are 33Ω to 100Ω. See application notes for guidelines regarding /MEM_WE resistor.
* Manufacturer’s data sheets are subject to change. Please confirm specifications before using this part.
Figure 108. Suggested AAL1gator II Memory Interface
Table 26. Recommended Worst-Case Parameters for Suggested Memory Interface
Number
Parameter
Min
Max
Unit
1
2
3
4
5
maximum tristatable address buffer output enable time (FCT244)
maximum tristatable address buffer output disable time (FCT244)
maximum tristatable address buffer propagation delay (FCT244)
maximum bidirectional tristatable data latch output enable time (FCT646)
maximum bidirectional tristatable data latch output disable time (FCT646)
1
1
1
8
8
ns
ns
ns
ns
ns
8
10
10
ꢀꢈꢄ
PMC [ PMC-SIERRA, INC ]
