PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
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AAL1 SAR Processor
8.11 Timing Requirements On External Logic for RAM and Microprocessor Interface
Microprocessor accesses are controlled by the AAL1gator II. To properly access the
AAL1gator II and the external memory, the AAL1gator II must be supported with a tristatable
address buffer and a bidirectional, tristatable data latch.
The RAM and microprocessor interface has been optimized to work with a pair of 128K x 16
SRAMs, a pair of FCT646s, and a few FCT244s, as shown in Figure 108 on page 195. Due to the
asynchronous timing of these parts, the speed of the interface, and the interleaving of different
types of read and write operations, the address, data, and control signals are skewed with respect
to each other to provide the delicate balance that is required.
It is strongly recommended that the architecture shown in Figure 108 on page 195 is followed,
especially if this interface is running near maximum speed. The components should also be placed
near each other. If slower speeds or faster parts are used, alternative architectures can be used, as
long as all timing parameters are met. Note that the capacitance for the timings given assumes the
architecture shown. Other configurations may have different loadings. Refer to section 8.6
“Board Requirements for the SRAM Interface” on page 174 for important timing informa-
tion regarding this interface.
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PMC [ PMC-SIERRA, INC ]
