PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Table 26. Recommended Worst-Case Parameters for Suggested Memory Interface (Continued)
Number
Parameter
Min
Max
Unit
6
minimum bidirectional tristatable data latch data setup to clock (FCT646)
minimum bidirectional tristatable data latch data hold to clock (FCT646)
maximum bidirectional tristatable data latch propagation delay (FCT646)
maximum RAM access delay from address stable and chip select active
minimum RAM data hold from address change
minimum RAM data hold from /OE or /CS high
maximum RAM output enable delay
5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
10
15
9
10
10
11
12
13
14
15
16
17
18
2
0
7
7
minimum RAM data setup to write clock
minimum RAM data hold to write clock
0
minimum RAM address hold to write clock
0
minimum RAM write enable minimum pulse width
minimum RAM address setup to write start
10
1
minimum RAM address setup to write end
12
6
maximum RAM output disable delay
The numbers in Table 26 are used in Figure 109 to Figure 112 on page 197 to show the suggested
memory interface timing relationships.
1
2
FCT244 /G
Y
3
A
Figure 109. Address Buffer (FCT244) Timing
ꢀꢈꢅ
PMC [ PMC-SIERRA, INC ]
