PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
WAC-121-A
Description
The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1,
E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate
(CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration,
the user data, and the statistics. The device provides a microprocessor interface for configuration,
management, and statistics gathering. PMC-Sierra also offers a software device control package
for the AAL1gator II device.
FEATURES
Circuit Interface Features
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Provides AAL1 segmentation and reassembly of eight 2 Mbit/s data streams or one
45 Mbit/s or less data stream.
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Supports 256 Virtual Channels (VCs) (32 per line).
Supports n × 64 structured data format.
Supports arbitrary timeslot-to-VC mappings, including alternating timeslots.
Provides Common Channel Signaling (CCS) and Channel Associated Signaling (CAS)
configuration options.
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Provides per-VC data and signaling conditioning in both the transmit and the receive
directions.
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Arbitrates a 16-bit microprocessor interface to a 128K × 16 (12 ns) SRAM.
Supports multicast connections, ATM Monitoring (AMON), Remote Monitoring
(RMON), and ATM Circuit Steering (ACS).
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Supports adaptive clocking in Structured Data Format, Frame-based (SDF-FR),
Structured Data Format, Multiframe-based (SDF-MF), and Unstructured Data Format,
Multiple Line (UDF-ML) modes.
Transmit Cell Interface Features
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Provides an ATM-layer or PHY-layer 33 MHz UTOPIA interface. Both Single PHY
(SPHY) and Multi-PHY (MPHY) modes are supported.
Provides per-VC transmit queueing.
Provides a calendar queue service algorithm that produces minimal Cell Delay Variation
(CDV).
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Provides a supervisory transmit buffer for Operations, Administration, and Maintenance
(OAM), and for ATM signaling.
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Generates pointers for structured data transmission.
Provides sequence number and sequence number protection generation.
Provides partially filled cell generation with the length configurable on a per-VC basis.
Generates and transmits Synchronous Residual Time Stamp (SRTS) values for
unstructured modes.
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Built-in transmit line clock generation based on received SRTS values, receive line clock,
or a nominal frequency.
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PMC [ PMC-SIERRA, INC ]
