PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Figure 1 shows a simple block diagram of the AAL1gator II.
Cell Service Decision (CSD)
Transmit Frame Transfer
Controller (TFTC)
Transmit Adaptation Layer
Processor (TALP)
Transmit UTOPIA Interface
Block (TUTOPIA)
Output to
UTOPIA
Input from
DS Line
Memory Interface and
Arbitration Controller (MIAC)
To External Memory
Receive Frame Transfer
Controller (RFTC)
Receive Adaptation Layer
Processor (RALP)
Receive UTOPIA Interface
Block (RUTOPIA)
Input from
UTOPIA
Output to
DS Line
Microprocessor Control Bus
Figure 1. AAL1gator II Block Diagram
Figure 2 shows a system block diagram of the AAL1gator II connected to eight 2 Mbit/s data
streams.
UTOPIA Interface
SRAM
AAL1gator II
(PM73121)
Address/Data
Buffer Control
2 Mbit/s
T1/E1 Framer
Buffers
Microprocessor Strobes
Microprocessor Address and Data
Figure 2. Block Diagram of the AAL1gator II Connected to Eight 2 Mbit/s Data Streams
Figure 3 shows a system block diagram of the AAL1gator II connected to one 45 Mbit/s data
stream.
UTOPIA Interface
SRAM
AAL1gator II
45 Mbit/s
DS3/E3 Framer
Address/Data
Buffer Control
(PM73121)
Buffers
Microprocessor Strobes
Microprocessor Address and Data
Figure 3. Block Diagram of the AAL1gator II Connected to One 45 Mbit/s Data Stream
ꢂ
PMC [ PMC-SIERRA, INC ]
