PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
7.6.10 MATH_TBL
Organization: 8 K words
Base address: 0C000h
Index: 1h
Type: Read/Write
Function: The math table must be loaded into SRAM on every power cycling, except in
UDF-HS mode, in which case the math table is not used. The math table stores the
results of five different mathematical operations.
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DIV_OP performs the integer divide and roundup-to-next integer operation. The num-
ber of integer credits (six bits) is divided by the number of channels (five bits). These
two fields are concatenated to form an 11-bit address into the table. The result is an
8-bit integer.
MOD_ADD_OP adds the results of the frame location to the frame offset. In the case
of T1 structured data, the mod is 120. All others use a module 128. The result is a 7-bit
integer. A 7-bit frame value is concatenated with a 6-bit frame increment value to form
a 13-bit address.
MULT_OP determines the number of earned integer credits for next service time. It is
obtained by multiplying the number of channels by the frame increment value. A 6-bit
frame value is concatenated with a 5-bit channel count to create an 11-bit address.
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T1_MF_DIV_OP determines the number of 1/8 multiframes and the remainder of the
division given a frame count for the T1 mode of operation.
E1_MF_DIV_OP determines the number of 1/8 multiframes and the remainder of the
division given a frame count for the E1 mode of operation.
Format: The four values resulting from the math operations are stored in the same table, as
shown in Figure 85.
Field (Bits)
Description
This table is available in the Software Driver available at http://www.pmc-sierra.com.
NOTE: The AAL1gator II uses a different math table than previous versions of the chip. The
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PMC [ PMC-SIERRA, INC ]
