PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Figure 5
- External Analog Receive Interface Circuit
V
DD
R1
RAVD
RAS
1:N
T
(Zin = 10kΩ
± 10%)
R2
R
REF
RRC
0.1 µF
± 10%
RAVS
47 nF
±10%
316 kΩ ±10
Notes:
1. All capacitors ceramic
2. Recommended Transformers:
BH Electronics 500-1775 (1:1:1);
Pulse Engineering PE 64931 (1:1:1); or
Pulse Engineering PE 65341 (1:1:1) (for extended temp range)
3. Alternatively, a dual part containing both the 1:2CT & 1:1.36 transformers can be used, i.e.:
BH Electronics 500-1777;
Pulse Engineering PE64952; or
Pulse Engineering PE65774 (for extended temp range)
The RSLC block can be disabled by strapping the receive analog power pin,
RAVD to ground. When RLSC is disabled, the E1XC accepts RZ input pulses on
the RDP/RDD and RDN/RLCV pins.
9.3
Clock and Data Recovery (CDRC)
The Clock and Data Recovery function is provided by a Data and Clock
Recovery (CDRC) block that provides clock and PCM data recovery, HDB3
decoding, bipolar violation detection, and loss of signal detection. The CDRC
block recovers the clock from the incoming RZ data pulses using a digital phase-
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PMC [ PMC-SIERRA, INC ]
