PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Pin Name Type
Pin No.
Function
PQFP PLCC
73 4
TCLKI
Input
Transmit Clock Input (TCLKI). This
input signal is used to generate the
TCLKO clock signal. Depending upon
the configuration of the E1XC, TCLKO
may be derived directly from TCLKI by
dividing TCLKI by 8, or TCLKO may
be derived from TCLKI after jitter
attenuation and frequency
multiplication (default is a frequency
ratio of one). If TCLKI is jitter-free
when divided down to 8 kHz, then it is
possible to derive TCLKO from TCLKI
when TCLKI is a multiple of 8 kHz (i.e.
Nx8 kHz, for N equals 1 to 256). The
E1XC may be configured to ignore the
TCLKI input and utilize BTCLK or
RCLKO instead. RCLKO is also
substituted for TCLKI if line loopback
is enabled.
XCLK/
Input
78
9
Crystal Clock Input (XCLK). This
signal provides timing for many
portions of the E1XC. Depending on
the configuration of the E1XC, XCLK
is nominally a 49.152 MHz or 16.384
MHz, 50% duty cycle clock. When
transmit clock generation or jitter
attenuation is not required, XCLK may
be driven with a 16.384 MHz clock.
When transmit clock generation or
jitter attenuation are required, XCLK
must be driven with a 49.152 MHz
clock.
VCLK
Vector Clock (VCLK). The VCLK
signal is used during E1XC production
test to verify internal functionality.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
