PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Pin Name Type
Pin No.
Function
PQFP PLCC
67 66
TDLCLK/ Output
Transmit Data Link Clock (TDLCLK).
The TDLCLK signal is available on this
output when the internal HDLC
transmitter (XFDL) is disabled from
use. The rising edge of TDLCLK is
used to sample the data stream
contained on the TDLSIG input. When
the E1XC is not configured to insert a
data link, the TDLCLK output is held
low.
TDLUDR
Transmit Data Link Underrun
(TDLUDR). The TDLUDR signal is
available on this output when XFDL is
enabled. TDLUDR goes high when
the processor has failed to service the
TDLINT interrupt before the transmit
buffer is emptied.
TCLKO
Output
72
3
Transmit Clock Output (TCLKO). The
TDP, TDN, and TDD outputs may be
enabled to be updated on the rising or
falling edge of TCLKO. The TAP and
TAN outputs are also driven with
timing derived from TCLKO. TCLKO is
a 2.048 MHz clock that is adequately
jitter and wander free in absolute
terms to permit an acceptable G.703
2048 kbit/s signal to be generated.
Depending on the configuration of the
E1XC, TCLKO may be derived from
TCLKI, RCLKO, or BTCLK, with or
without jitter attenuation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
30
PMC [ PMC-SIERRA, INC ]
