PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 30H:TPSC Block Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
IND
X
X
X
X
X
X
0
R/W
R/W
PCCE
0
This register allows selection of the microprocessor read access type and output
enable control for the Transmit Per-channel Serial Controller.
IND:
The IND bit controls the microprocessor access type: either indirect or direct.
The IND bit must be set to logic 1 for proper operation. When the E1XC is
reset, the IND bit is set low, disabling the indirect access mode.
PCCE:
The PCCE bit enables the per-timeslot functions. When the PCCE bit is set
to a logic 1, each timeslot's Data Control byte and IDLE Code byte are
passed on to the TRAN block. When the PCCE bit is set to logic 0, the per-
timeslot functions are disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
138
PMC [ PMC-SIERRA, INC ]
