PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 2CH:TS16 AIS Alarm Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
TS16AISE
TS16AISI
TS16AIS
Unused
X
0
R/W
R
X
X
X
X
X
X
R
Unused
Unused
Unused
Reading this register returns the current value of the time slot 16 AIS status.
The TS16 AIS alarm algorithm accumulates the occurrences of T16AISD (TS16
AIS detection) events. T16AISD is defined as two consecutive all ones time slot
16 bytes while out of signalling multiframe. Each interval with a valid TS16 AIS
presence indication increments an interval counter which declares TS16 AIS
Alarm when 22 valid intervals have been accumulated. An interval with no valid
TS16 AIS presence indication decrements the interval counter; the TS16 AIS
Alarm declaration is removed when the counter reaches 0. This algorithm
provides a 99.1% probability of declaring an TS16 AIS Alarm within 3.1 ms after
-3
loss of signalling multiframe detection in the presence of a 10 mean bit error
rate.
TS16AISE:
If the TS16AISE bit is a logic 1, an interrupt is generated when the TS16AIS
status bit changes state.
TS16AISI:
The TS16AISI bit is set high when the TS16AIS status bit changes state. It is
cleared when this register is read.
TS16AIS:
The TS16AIS bit is a logic one when an all ones condition has persisted in
time slot 16 for 3 ms. The bit returns to a logic zero when the time slot 16 AIS
condition has been absent for 3 ms.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
137
PMC [ PMC-SIERRA, INC ]
