PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 2BH: FRMR CRC Error Counter – MSB
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
OVR
NEWDATA
Unused
Unused
Unused
Unused
CRCE9
CRCE8
X
X
X
X
X
X
X
X
R
R
This register contains the most significant two bits of the 10-bit CRC error
counter value, updated every second.
NEWDATA:
The NEWDATA flag bit indicates that the counter register contents have been
updated with a new count value accumulated over the last 1 second interval.
It is set to logic 1 when the CRC error counter data is transferred into the
counter registers, and is reset to logic 0 when this register is read.This bit can
be polled to determine the 1 second timing boundary used by the FRMR.
OVR:
The OVR flag bit indicates that the counter register contents have not been
read within the last 1 second interval, and therefore have been over-written. It
is set to logic 1 if CRC error counter data is transferred into the counter
registers before the previous data has been read out, and is reset to logic 0
when this register is read.
This CRC error count is distinct from that of PMON because it is guaranteed to
be an accurate count of the number of CRC error in one second; whereas,
PMON relies on externally initiated transfers which may not be one second apart.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
136
PMC [ PMC-SIERRA, INC ]
