PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
LIST OFTABLES
TABLE 1 - RECOMMENDED RX NETWORK VALUES.................................41
TABLE 2 - NORMAL MODE REGISTER MEMORY MAP .............................63
TABLE 3 - TRANSMIT TIMING OPTIONS.....................................................87
TABLE 4 - XPLS CODE REGISTER MEMORY MAP..................................112
TABLE 5 - TPSC INDIRECT MEMORY MAP...............................................142
TABLE 6 - A-LAW DIGITAL MILLIWATT PATTERN......................................145
TABLE 7 - µ-LAW DIGITAL MILLIWATT PATTERN ......................................145
TABLE 8 - SIGX INDIRECT MEMORY MAP ...............................................162
TABLE 9 - TEST MODE REGISTER MEMORY MAP..................................187
TABLE 10 - E1XC DEFAULT SETTINGS.......................................................198
TABLE 11 - RSLC PERFORMANCE LIMITS ................................................216
TABLE 12 - RECOMMENDED RX NETWORK VALUES...............................218
TABLE 13 - ALTERNATIVE NETWORK RSLC PERFORMANCE LIMITS.....220
TABLE 14 - RECOMMENDED ALTERNATIVE NETWORK VALUES ............221
TABLE 15 - XPLS TYPICAL OUTPUT PULSE AMPLITUDES ......................221
TABLE 16 - BER REQUIRED FOR PMON COUNTER SATURATION ..........227
TABLE 17 - E1XC D.C. CHARACTERISTICS................................................232
TABLE 18 - MICROPROCESSOR READ ACCESS (FIGURE 36) ................234
TABLE 19 - MICROPROCESSOR WRITE ACCESS (FIGURE 37)...............237
TABLE 20 - BACKPLANE TRANSMIT INPUT TIMING (FIGURE 38)............239
TABLE 21 - XCLK=49.152MHZ INPUT (FIGURE 39)....................................240
TABLE 22 - TCLKI INPUT (FIGURE 40)........................................................241
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
