PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
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FEATURES
Integrates a full-featured E1 transceiver in a single device with analog
circuitry for receiving and transmitting G.703 2048 kbit/s compatible signals
and digital circuitry for terminating the duplex digital signal.
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Pin compatible with the PMC PM4341A T1 Framer/Transceiver device.
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Provides an 8-bit microprocessor bus interface for configuration, control, and
status monitoring.
Low power CMOS technology.
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Available in either a 68 pin PLCC or an 80 pin PQFP package.
The receiver section:
Provides analog circuitry for receiving a G.703 2048 kbit/s signal with up to 6
dB of cable attenuation. Direct digital inputs are also provided to allow for by-
passing the analog front-end.
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Recovers clock and data using a digital phase locked loop for high jitter
tolerance. A direct clock input is provided to allow clock recovery to be by-
passed.
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Accepts dual rail or single rail digital PCM inputs.
Supports HDB3 or AMI line code.
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Accepts gapped data streams to support higher rate demultiplexing.
Frames to a G.704 2048 kbit/s signal within 1 ms.
Frames to the signalling multiframe alignment when enabled.
Frames to the CRC multiframe alignment when enabled.
Provides loss of signal detection, and indicates loss of frame alignment
(OOF), loss of signalling multiframe alignment and loss of CRC multiframe
alignment.
Supports line and path performance monitoring according to ITU-T
recommendations. Accumulators are provided for counting:
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CRC-4 errors to 1000 per second;
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Far end block errors to 1000 per second;
Frame sync errors to 127 per second; and
Line code violations to 8191 per second.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
