PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 0DH: E1XC Master Reset
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
RESET
X
X
X
X
X
X
X
0
R/W
RESET:
The RESET bit implements a software reset. If the RESET bit is a logic 1, the
entire E1XC is held in reset. This bit is not self-clearing; therefore, a logic 0
must be written to bring the E1XC out of reset. Holding the E1XC in a reset
state effectively puts it into a low power, stand-by mode. A hardware reset
clears the RESET bit, thus deasserting the software reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
98
PMC [ PMC-SIERRA, INC ]
