PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0751H: TCFP Interrupt Indication
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R
R
R
FIFO_ERRI
FIFO_UDRI
XFERI
0
0
0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XFERI:
The XFERI bit indicates that a transfer of accumulated counter data has occurred. A logic 1 in
this bit position indicates that the transmitted cell/packet counter, transmitted byte counter,
and aborted packet counter holding registers have been updated. This update is initiated by
writing to one of the TCFP counter register locations, or initiating a global performance
monitor update by writing to register 0000H. XFERI is set to logic 0 when this register is
read.
FIFO_UDRI:
The FIFO_UDRI bit is set high when an attempt is made to read from the FIFO while it is
empty. This is considered a system error. This bit is set to logic 0 immediately after a read
to this register.
FIFO_ERRI:
This bit is set to one when an error is detected on the read side of the FIFO. This error can
be caused by an abnormal sequence of TSOP and TEOP signals or the assertion of
FIFO_ERR. This can normally be caused by a previous FIFO overrun or underrun condition
or a user asserted error from the POS-PHY L3 interface. This bit is reset immediately after a
read to this register.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
328
PMC [ PMC-SIERRA, INC ]
