PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the transmitted packet/cell counter, transmitted byte
counter, and aborted packet counter holding registers. When XFERE is set to logic 1, the
interrupt is enabled.
FIFO_UDRE:
The FIFO_UDRE bit enables the generation of an interrupt due to a FIFO underrun. When
FIFO_UDRE is set to logic 1, the interrupt is enabled the signal INTB will be set to logic 0
whenever FIFO_UNRI is set to logic 1.
FIFO_ERRE:
The FIFO_ERRE bit enables the generation of an interrupt due to a FIFO error. When
FIFO_ERRE is set to logic 1, the interrupt is enabled and the signal INTB will be set to logic 0
whenever FIFO_ERRI is set to logic 1.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
327
PMC [ PMC-SIERRA, INC ]
