PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
PUNEQI:
The path payload unequipped interrupt status (PUNEQI) bit is an event indicator. PUNEQI is
set to logic 1 to indicate any change in the status of PUNEQV (equipped to unequipped or
unequipped to equipped). The interrupt status bit is independent of the interrupt enable bit.
PUNEQI is cleared to logic 0 when this register is read.
PPDII:
The path payload defect indication interrupt status (PPDII) bit is an event indicator. PPDII is
set to logic 1 to indicate any change in the status of PPDIV (no defect to payload defect or
payload defect to no defect). The interrupt status bit is independent of the interrupt enable
bit. PPDII is cleared to logic 0 when this register is read.
PRDII:
The path remote defect indication interrupt status (PRDII) bit is an event indicator. PRDII is
set to logic 1 to indicate any change in the status of PRDIV (no defect to RDI defect or RDI
defect to no defect). The interrupt status bit is independent of the interrupt enable bit. PRDII
is cleared to logic 0 when this register is read.
PERDII:
The path enhanced remote defect indication interrupt status (PERDII) bit is an event indicator.
PERDII is set to logic 1 to indicate any change in the status of PERDIV (no defect to ERDI
defect or ERDI defect to no defect). The interrupt status bit is independent of the interrupt
enable bit. PERDII is cleared to logic 0 when this register is read.
COPERDII:
The change of path enhanced remote defect indication interrupt status (COPERDII) bit is an
event indicator. COPERDII is set to logic 1 to indicate a new ERDI-P value. The interrupt
status bit is independent of the interrupt enable bit. COPERDII is cleared to logic 0 when this
register is read.
PBIPEI:
The path BIP-8 error interrupt status (PBIPEI) bit is an event indicator. PBIPEI is set to logic
1 to indicate a path BIP-8 error. The interrupt status bit is independent of the interrupt enable
bit. PBIPEI is cleared to logic 0 when this register is read.
PREIEI:
The path REI error interrupt status (PREIEI) bit is an event indicator. PREIEI is set to logic 1
to indicate a path REI error. The interrupt status bit is independent of the interrupt enable bit.
PREIEI is cleared to logic 0 when this register is read.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
214
PMC [ PMC-SIERRA, INC ]
