PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
PL3EN:
The POS-PHY Level 3 Select bit (POSL3) is OR’ed with the POSL3_UL3B pin to select POS-
PHY Level 3 mode on the system interface. When POSL3 or POSL3_UL3B are logic 1, the
system bus operates in POS-PHY Level 3 mode. When both POSL3 and POSL3_UL3B are
logic 0, the bus operates as a UTOPIA Level 3 bus. Reading this bit gives the mode of the
bus, (ie, the OR of the pin and the bit). The default state of this register bit is logic 0.
DISCOR:
The DISCOR bit is used to globally disable ATM single-bit HCS error correction. When
DISCOR is set to logic 1, HCS error correction is globally disabled. When DISCOR is set to
logic 0, HCS error correction is dependent on the RCFP Configuration register. By default,
HCS error correction is enabled in the RCFP.
RXDINV:
The receive inversion RXDINV bit controls the polarity of the receive data. When RXDINV is
set high, the polarity of the RXD+/- is inverted. When RXDINV is set low, the RXD+/- inputs
operate normally.
TXDINV:
The transmit inversion TXDINV bit controls the polarity of the transmit data. When TXDINV is
set high, the polarity of the TXD+/- is inverted. When TXDINV is set low, the TXD+/- outputs
operate normally.
ARESET:
The ARESET bit allows the analog circuitry in the S/UNI-2488 to be reset under software
control. If the ARESET bit is a logic one, all the S/UNI-2488 analog circuitry is held in reset.
This bit is not self-clearing. Therefore, a logic zero must be written to bring the S/UNI-2488
out of reset. Holding the S/UNI-2488 in a reset state places it into a low power, analog stand-
by mode. A hardware reset clears the ARESET bit, thus negating the analog software reset.
DRESET:
The DRESET bit allows the digital circuitry in the S/UNI-2488 to be reset under software
control. If the DRESET bit is a logic one, all the S/UNI-2488 digital circuitry is held in reset.
This bit is not self-clearing. Therefore, a logic zero must be written to bring the S/UNI-2488
out of reset A hardware reset clears the DRESET bit, thus negating the digital software reset.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
101
PMC [ PMC-SIERRA, INC ]
