PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
10.17.1 Transmit UTOPIA Level 3 Interface
The UTOPIA Level 3 compliant interface accepts a write clock (TFCLK), a write enable signal
(TENB), the start of a cell (TSOC) indication and the parity bit (TPRTY) when data is written to the
transmit FIFO (using the rising edges of the TFCLK). To reduce FIFO latency, the FIFO depth at
which TCA indicates “full” can be configured from the TXSDQ. If the programmed depth is less
than the TXSDQ FIFO capacity, more than one cell may be written after TCA is deasserted as the
TXSDQ FIFO still allows the “maximum” cells to be stored in its FIFO. The interface provides the
transmit cell available status (TCA) which can transition from "available" to "unavailable" when
the transmit FIFO is near full or when the FIFO is full and can accept no more writes. The TCFP
cell processor automatically transmit idle cells until a full cell is available to be transmitted.
10.17.2 Transmit POS-PHY Level 3 Interface
The POS-PHY Level 3 compliant interface accepts a write clock (TFCLK), a write enable signal
(TENB), the start of packet (TSOP) indication, the end of packet (TEOP) indication, errored
packet (TERR) indication and the parity bit (TPRTY) when data is written to the transmit FIFO
(using the rising edges of the TFCLK). The TPA signal notifies that the transmit FIFO is not full
(the POS processor will not start transmitting a packet until a programmable number of bytes for
a single packet or the entire packet is in the FIFO). The TMOD signal (Transmit Mod) is provided
to indicate whether 1, 2, 3, or 4 bytes are valid of the final word transfer (TEOP is asserted). A
packet may be aborted by asserting the TERR signal at the end of the packet. The interface also
indicates FIFO overruns via a maskable interrupt and register bits. The TCFP HDLC processor
automatically transmits idle flag characters until sufficient data is available in the transmit TXSDQ
to start transmission.
10.18 SONET/SDH Bit Error Rate Monitor (SBER)
The SBER block provides two independent bit error rate monitoring circuits (BERM block). It is
used to monitor the Multiplexer Section BIP (B1) with one BERM block dedicated to monitor the
Signal Degrade (SD) alarm and the other BERM block dedicated to monitor the Signal Fail (SF)
alarm. These alarm can then be used to control system level features such as Automatic
Protection Switching (APS).
The BERM block utilizes a sliding window based algorithm.
10.19 SONET/SDH Alarm Reporting Controller (SARC)
The SARC block receives all the section, line, and path defects detected by the receive overhead
processors and, according to user specific configuration, generates consequent action
indications.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
80
PMC [ PMC-SIERRA, INC ]
