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PM5380-BI 参数 Datasheet PDF下载

PM5380-BI图片预览
型号: PM5380-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 440 页 / 2124 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet  
Released  
Figure 7 CRC Decoder  
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10.7.6 Performance Monitor  
The Performance Monitor consists of four 16-bit saturating error event counters and one 24-bit  
saturating received good packet counter. One of the error event counters accumulates FCS  
errors. The second error event counter accumulates minimum length violation packets. The  
third error event counter accumulates maximum length violation packets. The fourth error  
event counter accumulates aborted packets. The 24-bit receive good packet counter counts all  
error free packets.  
Each counter may be read through the microprocessor interface. Circuitry is provided to latch  
these counters so that their values can be read while simultaneously resetting the internal  
counters to 0 or 1, whichever is appropriate, so that a new period of accumulation can begin  
without loss of any events. The counters should be polled at least once per second so error  
events will not be missed.  
The RXFP monitors the packets for both minimum and maximum length errors. When a packet  
size is smaller than MINPL[7:0], the packet is marked with an error but still written into the  
FIFO. Malformed packets, that is packets that do not at least contain the FCS field plus one  
byte, are treated differently. If a malformed packet is received and FCS stripping is enabled, the  
packet is discarded, not written in the FIFO, and counted as a minimum packet size violation. If  
a malformed packet is received and FCS stripping is disabled, it is written into the FIFO since,  
in this case, the misformed packet criteria is reduced to one byte, but will still count as a  
minimum packet size violation. When the packet size exceeds MAXPL[15:0] the packet is  
marked with an error and the bytes beyond the maximum count are discarded.  
10.8 Transmit Line Interface (CSPI)  
The Transmit Line Interface allows to directly interface the S/UNI-8x155 with optical modules  
(ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel  
to serial conversion on each outgoing 155.52 Mbit/s data stream.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC- 2010299, Issue 2  
79  
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