S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
10.8.1 Clock Synthesis
The transmit clock is synthesized from a 77.76 MHz reference by the clock synthesis unit
(CSU). The transfer function yields a typical low pass corner of 1 MHz, above which reference
jitter is attenuated at least 20 dB per octave. The design of the loop filter and PLL is optimized
for minimum intrinsic jitter. With a jitter free 77.76 MHz reference, the intrinsic jitter is
typically 0.006 UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency.
The REFCLK reference should be within ±20 ppm to meet the SONET/SDH free-run accuracy
requirements specified in GR-253-CORE.
10.8.2 Parallel to Serial Converter
The Parallel to Serial Converter (PISO) converts each transmit byte serial stream to a bit serial
stream. The transmit bit serial streams appear on the TXD[7:0]+/- PECL outputs.
10.9 Transmit Section Overhead Processor (TSOP)
The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2),
scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion. In addition, it
may insert the section data communication channel provided serially on the transmit DCC
inputs.
10.9.1 Line AIS Insert
Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 before scrambling
except for the section overhead. The Line AIS Insert Block substitutes all ones as described
when enabled by the TLAIS input or through an internal register accessed through the
microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to
frame boundaries.
10.9.2 Data Link Insert
The Data Link Insert Block inserts the section data communication channel (bytes D1, D2, and
D3) into the STS-3c/STM-1 stream when enabled by an internal register accessed via the
common bus interface. The bytes to be inserted are serially input on the associated TDCC
signal at a nominal 192 kbit/s rate. Timing for upstream processing of the data communication
channel is provided by the TDCLK signal. TDCLK is derived from a 216 kHz clock that is
gapped to yield an average frequency of 192 kHz.
10.9.3 BIP-8 Insert
The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the
transmit stream.
The BIP-8 calculation is based on the scrambled data of the complete STS-3c/STM-1 frame.
The section BIP-8 code is based on a bit interleaved parity calculation using even parity.
Details are provided in the references. The calculated BIP-8 code is then inserted into the B1
byte of the following frame before scrambling. BIP-8 errors may be continuously inserted
under register control for diagnostic purposes.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
80
PMC [ PMC-SIERRA, INC ]
