S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0D1, 0x1D1, 0x2D1, 0x3D1, 0x4D1, 0x5D1, 0x6D1, 0x7D1:
WANS Interrupt and Status
Bit
Type
Function
Unused
Unused
Unused
Unused
Unused
Unused
RPHALGN
TIMI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
TIMI:
The Timer Interrupt (TIMI) bit indicates a Timer Interrupt condition. This bit will be raised
at the beginning of the Phase Detector averaging period. In addition to indicating the
interrupt status, this bit can also be polled to synchronize read access to the WANS output
register. This interrupt can be masked using the INTEN bit of the configuration register. A
read access to the Interrupt & Status Register resets the value of this bit.
RPHALGN:
The Reference Phase Alignment (RPHALNG) bit indicates a Reference Phase Alignment
event. In normal operating mode, this bit remains to logic zero. Upon the occurrence of a
Reference Phase Alignment, this bit is set to logic one, indicating that the phase averaging
process was aborted and that the value of the Phase Word register is frozen to the previous
valid value. This bit is reset low after the completion of a valid phase averaging cycle.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
275
PMC [ PMC-SIERRA, INC ]
