S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0CE, 0x1CE, 0x2CE, 0x3CE, 0x4CE, 0x5CE, 0x6CE, 0x7CE:
TXFP Transmit Underrun/Error Aborted Frame Count LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TFERABF[7]
TFERABF[6]
TFERABF[5]
TFERABF[4]
TFERABF[3]
TFERABF[2]
TFERABF[1]
TFERABF[0]
X
X
X
X
X
X
X
X
Register 0x0CF, 0x1CF, 0x2CF, 0x3CF, 0x4CF, 0x5CF, 0x6CF, 0x7CF:
TXFP Transmit Underrun/Error Aborted Frame Count MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TFERABF[15]
TFERABF[14]
TFERABF[13]
TFERABF[12]
TFERABF[11]
TFERABF[10]
TFERABF[9]
TFERABF[8]
X
X
X
X
X
X
X
X
TRERABF[15:0]:
The TFERABF[15:0] bits indicate the number of FIFO underrun error aborted POS frames
read from the transmit FIFO and inserted into the transmission stream during the last
accumulation interval. FIFO underruns errors are caused when the FIFO runs empty and
the last byte read was not an end of packet or also when the FIFO overruns and corrupts the
end of packet/start of packet sequence (example: when another RSOP is high when
expecting an REOP). This is considered a system error and should not occur when the
system works normally. A write to any one of the TXFP Transmit User Aborted Frame
Counter registers loads the registers with the current counter value and resets the internal
counter to zero.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
273
PMC [ PMC-SIERRA, INC ]
