S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0D0, 0x1D0, 0x2D0, 0x3D0, 0x4D0, 0x5D0, 0x6D0, 0x7D0:
WANS Configuration
Bit
Type
R/W
Function
Reserved
Unused
Unused
Unused
FORCEREAC
AUTOREAC
INTEN
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
PHACOMPEN
PHACOMPEN:
The Phase Comparison Enable (PHACOMPEN) bit is used to enable the phase comparison
process. Setting this bit to a logic one will enable the phase comparison process. When set
low, the phase and reference period counters are kept in reset state, further disabling the
WANS process
INTEN:
The Interrupt Enable (INTEN) bit controls the generation of the interrupt signal. When set
high, this bit allows the generation of an interrupt signal at the beginning of the Phase
Detector averaging period. Setting this bit to logic zero disable the generation of the
interrupts.
AUTOREAC:
The Auto Reacquisition Mode Select (AUTOREAC) bit can be used to set the WANS to
automatic phase reacquisition mode. When operating in this mode, the WANS will
automatically align the phase sampling point toward the middle of the Phase Counter period
upon detection of two consecutive Phase Sample located on each side of the Phase Counter
wrap around value. Setting this bit to logic 1 enables the automatic reacquisition mode.
FORCEREAC:
The Force Phase Reacquisition (FORCEREAC) bit can be used to force a phase
reacquisition of the Phase Detector. A logic zero to logic one transition on this bit triggers a
phase reacquisition sequence of the Phase Detector. Setting this bit to logic zero allows the
Phase detector to operate normally.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
274
PMC [ PMC-SIERRA, INC ]
