S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0CB, 0x1CB, 0x2CB, 0x3CB, 0x4CB, 0x5CB, 0x6CB, 0x7CB:
TXFP Transmit Frame Count MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TFRAME[23]
TFRAME[22]
TFRAME[21]
TFRAME[20]
TFRAME[19]
TFRAME[18]
TFRAME[17]
TFRAME[16]
X
X
X
X
X
X
X
X
TFRAME[23:0]:
The TFRAME[23:0] bits indicate the number of POS frames read from the transmit FIFO
and inserted into the transmission stream during the last accumulation interval. This
counter does not count aborted frames. A write to any one of the TXFP Transmit Frame
Counter registers loads the registers with the current counter value and resets the internal
counter to zero.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
271
PMC [ PMC-SIERRA, INC ]
