S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0A0, 0x1A0, 0x2A0, 0x3A0, 0x4A0, 0x5A0, 0x6A0, 0x7A0:
RXFP Configuration
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
FCSPASS
Reserved
FCSSEL[1]
FCSSEL[0]
Reserved
DDSCR
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
1
0
FIFORST
FIFORST:
The FIFORST bit is used to reset the channel 256-byte receive buffer. When FIFORST is
set low, the channel buffer operates normally. When FIFORST is set high, the buffer is
immediately emptied and ignores writes. The buffer remains empty and continues to ignore
writes until a logic zero is written to FIFORST.
The FIFORST must be set high before the per-channel FIFO reset in the RUL3 is asserted.
The FIFORST must be set low after the per-channel FIFO rset in the RUL3 is deasserted.
DDSCR:
43
The DDSCR bit controls the descrambling of the frame payload with the polynomial x
+
1. When DDSCR is set low, frame payload descrambling is disabled. When DDSCR is set
high, payload descrambling is enabled.
FCSSEL[1:0]:
The Frame Control Sequence select (FCSSEL[1:0]) bits allow to control the FCS
calculation according to the table below. The FCS is calculated over the whole packet data,
after byte destuffing and descrambling.
FCSSEL[1:0]
FCS Operation
No FCS calculated
CRC-16.ISO-3309 (2 bytes)
CRC-32 (4 bytes)
Reserved
00
01
10
11
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
248
PMC [ PMC-SIERRA, INC ]
