S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x098, 0x198, 0x298, 0x398, 0x498, 0x598, 0x698, 0x798:
JAT Configuration #1
Bit
Type
R/W
Function
Reserved
Unused
Unused
FERRI
Default
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
0
R
R
R
R
RUN
Reserved
Reserved
Reserved
R/W
Reserved:
The reserved bit must be programmed to zero for proper operation.
RUN:
The JAT lock status register bit RUN indicates the JAT has found an initial delay line lock.
When the JAT is attempting to recover the incoming serial stream, RUN is set high. The
RUN register bit is cleared only by a system reset or a software reset.
FERRI:
The line loopback FIFO error status (FERRI) indicates that the 8-byte line loopback FIFO
has overrun or underrun. The FERRI bit is set high when the loopback FIFO corrupts the
transmit data stream due to a FIFO overrun or underrun. The FERRI bit clears when the
register is read, thus acknowledging the error has occurred.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
245
PMC [ PMC-SIERRA, INC ]
