S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Figure 35 Interfacing S/UNI-8x155 Line PECL Pins to 5.0V Devices..................................... 407
Figure 36 ECL Bias Voltage Generator Networks................................................................... 408
Figure 37 Interfacing S/UNI-8x155 APS PECL Pins to 5.0V Devices..................................... 409
Figure 38 Interfacing S/UNI-8x155 APS PECL Pins to 3.3V Devices..................................... 409
Figure 39 Interfacing S/UNI-8x155 APS PECL Pins to 5.0V ECL Buffer................................ 409
Figure 40 Transmit UTOPIA Level 3 System Interface Timing ............................................... 411
Figure 41 Receive UTOPIA Level 3 System Interface Timing ................................................ 412
Figure 42 Transmit POS Level 3 System Interface Timing..................................................... 413
Figure 43 Receive POS Level 3 System Interface Timing...................................................... 414
Figure 44 Transmit Line Data Link Clock and Data Insertion.................................................. 415
Figure 45 Transmit Section Data Link Clock and Data Insertion ............................................ 415
Figure 46 Receive Line Data Link Clock and Data Extraction ................................................ 416
Figure 47 Receive Section Data Link Clock and Data Extraction........................................... 416
Figure 48 Microprocessor Interface Read Timing................................................................... 421
Figure 49 Microprocessor Interface Write Timing ................................................................... 422
Figure 50 RSTB Timing Diagram ............................................................................................ 424
Figure 51 Transmit UTOPIA Level 3 System Interface Timing Diagram ................................ 425
Figure 52 Receive UTOPIA Level 3 System Interface Timing Diagram ................................. 426
Figure 53 Transmit POS-PHY Level 3 System Interface Timing ............................................ 428
Figure 54 Receive POS-PHY Level 3 System Interface Timing ............................................. 430
Figure 55 Transmit DCC Interface Timing............................................................................... 431
Figure 56 Receive DCC Interface Timing................................................................................ 432
Figure 57 Clock and Frame Pulse Interface Timing................................................................ 433
Figure 58 Input APS Port Jitter Tolerance................................................................................ 435
Figure 59 JTAG Port Interface Timing..................................................................................... 436
Figure 60 Mechanical Drawing 520 in Super Ball Grid Array (SBGA) ................................... 439
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
21
PMC [ PMC-SIERRA, INC ]
