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PM5380-BI 参数 Datasheet PDF下载

PM5380-BI图片预览
型号: PM5380-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 440 页 / 2124 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet  
Released  
List of Tables  
Table 1 Pointer Interpreter Event (Indications) Description ...................................................... 73  
Table 2 Pointer Interpreter Transition Description .................................................................... 73  
Table 3 HDLC Byte Sequences ................................................................................................ 78  
Table 4 HDLC Byte Sequences ................................................................................................ 85  
Table 5 Path Signal Label Mismatch Mechanism ..................................................................... 87  
Table 6 Path Signal Label Mismatch Mechanism ..................................................................... 87  
Table 7 Top Level Register Memory Map ................................................................................. 98  
Table 8 Per Channel Register Memory Map............................................................................. 99  
Table 9 System and APS Interface Register Memory Map..................................................... 105  
Table 10 APS Cross Connect and Aligner .............................................................................. 108  
Table 11 Receive Initiation Level Values ................................................................................ 254  
Table 12 Transmit Initiation Level Values ............................................................................... 266  
Table 13 Inter Packet Gaping Values...................................................................................... 267  
Table 14 Test Mode Register Memory Map............................................................................ 368  
Table 15 Instruction Register (Length - 3 bits)........................................................................ 371  
Table 16 S/UNI-8x155 Identification Register......................................................................... 371  
Table 17 S/UNI-8x155 Boundary Scan Register..................................................................... 371  
Table 18 Settings for SONET or SDH Operation.................................................................... 389  
Table 19 Recommended BERM settings ................................................................................ 390  
Table 20 Path RDI and Extended RDI Register Settings........................................................ 390  
Table 21 Channel Swizzle Configuration ................................................................................ 398  
Table 22 1+1 APS Configuration............................................................................................. 399  
Table 23 1:8 APS Configuration.............................................................................................. 399  
Table 24 Absolute Maximum Ratings...................................................................................... 417  
Table 25 D.C Characteristics .................................................................................................. 418  
Table 26 Power Requirements................................................................................................ 420  
Table 27 Microprocessor Interface Read Access (Figure 48)................................................. 421  
Table 28 Microprocessor Interface Write Access (Figure 49)................................................. 422  
Table 29 RSTB Timing (Figure 50) ......................................................................................... 424  
Table 30 OC-3 Interface Timing............................................................................................... 424  
Table 31 Transmit UTOPIA Level 3 System Interface Timing (Figure 51).............................. 425  
Table 32 Receive UTOPIA Level 3 System Interface Timing (Figure 52)............................... 426  
Table 33 Transmit POS-PHY Level 3 System Interface Timing (Figure 53)........................... 427  
Table 34 Receive POS-PHY Level 3 System Interface Timing (Figure 54)............................ 429  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC- 2010299, Issue 2  
22  
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