S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x02A, 0x12A, 0x22A, 0x32A, 0x42A, 0x52A, 0x62A, 0x72A:
SSTB Indirect Address Register
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
This register supplies the address used to index into section trace identifier buffers. Writing to
this register triggers the indirect read/write access to the trace buffer.
A[7:0]:
The indirect read address bits (A[7:0]) indexes into the path trace identifier buffers.
Addresses 0 to 63 reference the transmit message buffer which contains the identifier
message to be inserted into the transmit stream.
Addresses 64 to 127 reference the receive accepted message page. A receive message is
accepted into this page when it is received unchanged three or five times consecutively as
determined by the PER5 bit setting.
Addresses 128 to 191 reference the receive capture page while addresses 192 to 255
reference the receive expected page. The receive capture page contains the identifier bytes
extracted from the receive stream. The receive expected page contains the expected trace
identifier message down-loaded from the microprocessor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
166
PMC [ PMC-SIERRA, INC ]
