S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x01F, 0x11F, 0x21F, 0x31F, 0x41F, 0x51F, 0x61F, 0x71F:
RLOP Line FEBE MSB
Bit
Type
Function
Unused
Unused
Unused
Unused
LFE[19]
LFE[18]
LFE[17]
LFE[16]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
LFE[19:0]
Bits LFE[19:0] represent the number of line FEBE errors (individual or block) that have
been detected since the last time the error count was polled. The error count is polled by
writing to any of the RLOP Line BIP-24 Register or Line FEBE Register addresses. Such a
write transfers the internally accumulated error count to the Line FEBE Registers within
approximately 7 µs and simultaneously resets the internal counter to begin a new cycle of
error accumulation.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
155
PMC [ PMC-SIERRA, INC ]
