PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
9.4 Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and
the logic required to connect to the microprocessor interface. The normal mode
registers are required for normal operation, and test mode registers are used to
enhance the testability of the TUDX. The register set is accessed as follows:
Table 1
- Register Memory Map
Register
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H-1FH
TUDX Master Configuration
TUDX Connection Memory Control
TUDX Clock Monitor
TUDX Master Reset/Revision ID
TUDX Parity Configuration
TUDX Parity Error Interrupt Enable
TUDX Parity Error Interrupt Status
TUDX Systolic Delay Control
Left Switch Element Connection Address High
Left Switch Element Connection Address Low
Left Switch Element Connection Data High
Left Switch Element Connection Data Low
Right Switch Element Connection Address High
Right Switch Element Connection Address Low
Right Switch Element Connection Data High
Right Switch Element Connection Data Low
TUDX Master Test
Reserved for Test
For all register accesses, CS1B and CS2B must be low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
27
PMC [ PMC-SIERRA, INC ]
