PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
pointer adjustments are absorbed into VT or TU pointer adjustments such that
the resulting STS-3 or STM-1 frame has its VTs or TUs occupying fixed,
appropriately phase aligned positions with respect to the overall transport
envelope frame, ready for switching.
The TUDX consists of two switching elements, each containing two time
switches, which results in a 2 by 2 array of time switches. Data from each of the
DINT and DINB buses is distributed and written into the two time switches in the
corresponding row. Data is collected for output on the DOUTL and DOUTR
buses from each of the two time switches in the corresponding column or
switching element, or from the associated SINL or SINR bus. The source of data
is programmable on a per timeslot basis within the switching elements. As only
one time switch in a column can source data during a given timeslot, time switch
outputs are powered down, rather than outputting data, 50% of the time.
In addition to implementing cross-connections, the switching elements are also
capable of inserting programmable idle code into outgoing timeslots. This idle
code is arbitrarily programmable on a per timeslot basis and thus through proper
programming, a fixed, arbitrary idle code can be inserted into any outgoing VT or
TU. This capability can be used to insert tributary path AIS or to insert fixed
codes used for system diagnostic purposes.
The switching elements are implemented in a classical manner with each having
a pair of data memories, a common connection memory, timing generator, output
multiplexer, and common bus interface.
9.3.1 Data Memories
The data memories each consist of two 270 x 8 RAMs implementing a double
buffered switch core. During each switching frame, data is written into sequential
locations in one page of memory, and read from the other page of memory
based on a list of addresses provided by the connection memory. At each
switching frame boundary (every 270 bytes) the function of the two memory
pages is reversed. The data memory is 8 bits wide to allow byte wide data to be
routed through the switching element. Two data memories are required, one for
each of the input buses connected to the switching element.
9.3.2 Connection Memory
The connection memory consists of a double buffered 270 x 13 RAM. During
each switching frame, information is sequentially read from the active memory
page and used to generate the read addresses for the data memory and control
the output multiplexer. Either connection memory can be written to or read from
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25
PMC [ PMC-SIERRA, INC ]
