PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
via the common bus interface and thus its contents are programmable. In this
manner, the switching action of the data memory and output multiplexer are
programmable on a per timeslot basis. Normally one would only write to the
inactive page, performing all the programming required to implement ones
desired connections, and then trigger a page swap at a frame boundary. Use of
a double buffered connection memory and active page swapping allows tributary
connections (which are implemented as group connections of 576 kbit/s
timeslots) to be coherently made or broken.
9.3.3 Timing Generator
The timing generator consists of a frame counter and clock dividers. Buffered
versions of the various derived clocks are distributed to other blocks within the
switching element as are several phase delayed versions of the frame count, as
required in such a pipelined processing structure.
9.3.4 Output Multiplexer
The output multiplexer consists of logic that selects the source of information to
be output from the switching element. Such selection is controlled on a per
timeslot basis by the connection memory and is thus programmable. Output data
can be routed from the data memory, from the lower order bits of the connection
memory, or a null value can be inserted when no connection is being made. The
null value is chosen on the fly to minimize power dissipation. The ability to
source data from the connection memory itself is how programmable idle code
insertion is provided. During those timeslots when programmable idle code is
being inserted or no connection is being made through the switching element,
the reading of data from the data memory is suppressed in order to save power.
In addition to its selection function, the output multiplexer also re-times control
signals sourced by the connection memory that are used to control the output
bus formatter of the complete device.
9.3.5 Common Bus Interface
The common bus interface allows microprocessor access to the switching
element connection memory. Access is indirect, via registers located in the
common bus interface. Each connection memory access takes up to eight SCLK
cycles to complete as circuitry waits for opportunities when the connection
memory locations in question are not being accessed during the normal course
of switching element operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
