PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
9
FUNCTIONAL DESCRIPTION
9.1 Input Bus Formatter
The input bus formatter captures data sampled on the DINT and DINB buses
and distributes this data to the two switching elements within the TUDX. The
input bus formatter also re-times this captured data, delaying it 5 clock cycles
and outputs copies of the information from the DINT and DINB buses on the
SOUTT and SOUTB buses, respectively. When systolic interconnect is not used,
the SOUTT and SOUTB buses can be held in a high impedance mode to save
power by strapping the SOBEB input appropriately.
For systolic array applications, a programmable delay element provides
additional delay of 5, 10, or 15 clock cycles in the DINT and DINB data paths or
in the SOUTT and SOUTB data paths. For more information on the systolic array
application, see the Application Examples section.
The input bus formatter also provides timing signals for the other blocks within
the TUDX. The system clock, SCLK, is buffered and distributed to the switching
elements and the output bus formatter. Frame pulses for the incoming and
outgoing data streams, IFP and OFP, are generated with alignment dictated by
the system frame pulse input, SFP. These frame pulses are buffered and
distributed to the switching elements. One can select whether the SFP input will
generate a coincident IFP or OFP pulse using the OFSEB configuration input.
This option is useful when constructing larger switches using arrays of TUDX
devices. The input bus formatter generates the IFP and OFP outputs. Proper
generation of IFP and OFP requires that the input bus formatter be initialized
once per SONET/SDH frame (125 µs) by a pulse on the SFP input. In the
absence of a periodic SFP input, outputs IFP and OFP are not generated
correctly.
9.2 Output Bus Formatter
The output bus formatter selects the data to be output on the DOUTL and
DOUTR buses. This data is gathered from the switching elements or the SINL
and SINR buses, on a per timeslot basis, as programmed within the switching
elements. The output bus formatter also drives the COUTL and COUTR outputs
with control signals that are programmable, on a per timeslot basis, via the
switching elements. The delay from the SINL or SINR buses to the DOUTL or
DOUTR buses is 5 clock cycles. The delay from the DINT or DINB buses to the
DOUTL or DOUTR buses for a straight through connection (from each input
timeslot to its equivalent output timeslot) is 275 clock cycles (corresponding to
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
23
PMC [ PMC-SIERRA, INC ]
