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PM5365-PI 参数 Datasheet PDF下载

PM5365-PI图片预览
型号: PM5365-PI
PDF下载: 下载PDF文件 查看货源
内容描述: VT / TU映射器和M13多路复用器 [VT/TU MAPPER AND M13 MULTIPLEXER]
分类和应用: 复用器
文件页数/大小: 244 页 / 1139 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM5365 TEMAP  
DATASHEET  
PMC-1991148  
ISSUE 3  
HIGH DENSITY VT/TU MAPPER  
AND M13 MULTIPLEXER  
internal registers. Internal registers are also used to configure the DS3-FRMR.  
Access to these registers is via a generic microprocessor bus.  
9.10 Performance Monitor Accumulator (DS3-PMON)  
The Performance Monitor (PMON) Block interfaces directly with the DS3 Framer  
(DS3-FRMR). Saturating counters are used to accumulate:  
Sꢀ line code violation (LCV) events  
Sꢀ parity error (PERR) events  
Sꢀ path parity error (CPERR) events  
Sꢀ far end block error (FEBE) events  
Sꢀ excess zeros (EXZS)  
Sꢀ framing bit error (FERR) events  
Due to the off-line nature of the DS3 Framer, PMON continues to accumulate  
performance meters even while the DS3-FRMR has declared OOF.  
When an accumulation interval is signaled by a write to the PMON register  
address space, the PMON transfers the current counter values into  
microprocessor accessible holding registers and resets the counters to begin  
accumulating error events for the next interval. The counters are reset in such a  
manner that error events occurring during the reset period are not missed.  
When counter data is transferred into the holding registers, an interrupt is  
generated, providing the interrupt is enabled. If the holding registers have not  
been read since the last interrupt, an overrun status bit is set. In addition, a  
register is provided to indicate changes in the PMON counters since the last  
accumulation interval.  
Whenever counter data is transferred into the holding registers, an interrupt is  
generated, providing the interrupt is enabled. If the holding registers have not  
been read since the last interrupt, an overrun status bit is set.  
9.11 DS3 Transmitter (DS3-TRAN)  
The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the  
overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The  
T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats.  
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use  
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