STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
interval is "valid" if it contains AIS or IDLE, defined as the occurrence of less than
15 discrepancies in the expected signal pattern (1010... for AIS, 1100... for IDLE)
while valid frame alignment is maintained. This discrepancy threshold ensures
-3
the detection algorithms operate in the presence of a 10 bit error rate. For AIS,
the expected pattern may be selected to be: the framed "1010" signal; the
framed arbitrary DS3 signal and the C-bits all zero; the framed "1010" signal and
the C-bits all zero; the framed all-ones signal (with overhead bits ignored); or the
unframed all-ones signal (with overhead bits equal to ones). Each "valid" M-
frame causes an associated integration counter to increment; "invalid" M-frames
cause a decrement. With the "slow" detection option, RED, AIS, or IDLE are
declared when the respective counter saturates at 127, which results in a
detection time of 13.5 ms. With the "fast" detection option, RED, AIS, or IDLE
are declared when the respective counter saturates at 21, which results in a
detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time).
RED, AIS, or IDLE are removed when the respective counter decrements to 0.
DS3 Loss of Frame detection is provided as recommended by ITU-T G.783 with
programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to
assert LOF, the counter will integrate up when the framer asserts an Out of
Frame condition and integrates down when the framer de-asserts the Out of
Frame condition. Once an LOF is asserted, the framer must not assert OOF for
the entire integration period before LOF is deasserted.
Valid X-bits are extracted by the DS3-FRMR to provide indication of far end
receive failure (FERF). A FERF defect is detected if the extracted X-bits are
equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are
equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status
remains in its previous state. The extracted FERF status is buffered for 2 M-
frames before being reported within the DS3 FRMR Status register. This buffer
ensures a better than 99.99% chance of freezing the FERF status on a correct
value during the occurrence of an out of frame.
When the C-bit parity application is enabled, both the far end alarm and control
(FEAC) channel and the path maintenance data link are extracted. Codes in the
FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC
messages in the Path Maintenance Data Link are received by the Data Link
Receiver (RDLC).
The DS3-FRMR can be enabled to automatically assert the RAI indication in the
outgoing transmit stream upon detection of any combination of LOS, OOF or
RED, or AIS. The DS3-FRMR can also be enabled to automatically insert C-bit
Parity FEBE upon detection of receive C-bit parity error.
The DS3-FRMR may be configured to generate interrupts on error events or
status changes. All sources of interrupts can be masked or acknowledged via
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
75
PMC [ PMC-SIERRA, INC ]
