STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
9.14 M12 Multiplexer (MX12)
The MX12 M12 Multiplexer integrates circuitry required to asynchronously
multiplex and demultiplex four DS1 streams into, and out of, an M12 formatted
DS2 serial stream (as defined in ANSI T1.107 Section 7) and to support
asynchronous multiplexing and demultiplexing of three 2048 kbit/s into and out of
a G.747 formatted 6312 kbit/s high speed signal (as defined in CCITT Rec.
G.747).
When multiplexing four DS1 streams into an M12 formatted DS2 stream, the
MX12 TSB performs logical inversion on the second and fourth tributary streams.
Rate adaptation to the DS2 is performed by integral FIFO buffers, controlled by
timing circuitry. The FIFO buffers accommodate in excess of 5.0 UIpp of
sinusoidal jitter on the DS1 clocks for all jitter frequencies. X, F, M, and C bits
are also generated and inserted by the timing circuitry. Software control is
provided to transmit Far End Receive Failure (FERF) indications, DS2 AIS, and
DS1 payload loopback requests. The loopback request is coded by inverting one
of the three C-bits (the default option is compatible with ANSI T1.107a Section
8.2.1 and TR-TSY-000009 Section 3.7).Two diagnostic options are provided to
invert the transmitted F or M bits.
When demultiplexing four DS1 streams from an M12 formatted DS2, the MX12
performs bit destuffing via interpretation of the C-bits. The MX12 also detects
and indicates DS1 payload loopback requests encoded in the C-bits. As per
ANSI T1.107 Section 7.2.1.1 and TR-TSY-000009 Section 3.7, the loopback
command is identified as C3 being the inverse of C1 and C2. Because TR-TSY-
000233 Section 5.3.14.1 recommends compatibility with non-compliant existing
equipment, the two other loopback command possibilities are also supported. As
per TR-TSY-000009 Section 3.7, the loopback request must be present for five
successive M-frames before declaration of detection. Removal of the loopback
request is declared when it has been absent for five successive M-frames.
DS1 payload loopback can be activated or deactivated under software control.
During payload loopback the DS1 stream being looped back still continues
unaffected in the demultiplex direction. The second and fourth demultiplexed
DS1 streams are logically inverted, and all four demultiplexed DS1 streams can
be replaced with AIS on an individual basis.
Similar functionality supports CCITT Recommendation G.747. The FIFO is still
required for rate adaptation. The frame alignment signal and parity bit are
generated and inserted by the timing circuitry. Software control is provided to
transmit Remote Alarm Indication (RAI), high speed signal AIS, and the reserved
bit. A diagnostic option is provided to invert the transmitted frame alignment
signal and parity bit.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
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PMC [ PMC-SIERRA, INC ]
