STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
9.7 Pseudo Random Binary Sequence Generation and Detection (PRBS)
The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a
software selectable PRBS generator and checker for 211-1, 215-1 or 220-1 PRBS
polynomials for use in the T1 and E1 links. PRBS patterns may be generated in
either the transmit or receive directions, and detected in the opposite direction.
The PRBS block can perform an auto synchronization to the expected PRBS
pattern and accumulates the total number of bit errors in two 24-bit counters.
The error count accumulates over the interval defined by to the Global PMON
Update Register. When an accumulation is forced, the holding register is
updated, and the counter reset to begin accumulating for the next interval. The
counter is reset in such a way that no events are missed. The data is then
available in the Error Count registers until the next accumulation.
9.8 Pseudo Random Pattern Generation and Detection (PRGD)
The Pseudo Random Pattern Generator/Detector (PRGD) block is a software
programmable test pattern generator, receiver, and analyzer for the DS3
payload. Patterns may be generated in the transmit direction, and detected in
the receive direction. Two types of ITU-T O.151 compliant test patterns are
provided : pseudo-random and repetitive.
The PRGD can be programmed to generate any pseudo-random pattern with
length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in
length. In addition, the PRGD can insert single bit errors or a bit error rate
-1
-7
between 10 to 10 .
The PRGD can be programmed to check for the generated pseudo random
pattern. The PRGD can perform an auto synchronization to the expected pattern
and accumulates the total number of bits received and the total number of bit
errors in two 32-bit counters. The counters accumulate either over intervals
defined by writes to the Pattern Detector registers, upon writes to the Global
PMON Update Register or automatically once a second. When an accumulation
is forced, the holding registers are updated, and the counters reset to begin
accumulating for the next interval. The counters are reset in such a way that no
events are missed. The data is then available in the holding registers until the
next accumulation.
9.9 DS3 Framer (DS3-FRMR)
The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a
B3ZS-encoded signal and framing to the resulting DS3 bit stream. The
DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
73
PMC [ PMC-SIERRA, INC ]
