STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
In T1 mode each jitter attenuator generates its output clock by adaptively dividing
the 37.056 MHz XCLK signal according to the phase difference between the jitter
attenuated clock and the input reference clock. Jitter fluctuations in the phase of
the reference clock are attenuated by the phase-locked loop within each DJAT
so that the frequency of the jitter attenuated clock is equal to the average
frequency of the reference. To best fit the jitter attenuation transfer function
recommended by TR 62411, phase fluctuations with a jitter frequency above 6.6
Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase
fluctuations with frequencies below 6.6 Hz are tracked by the jitter attenuated
clock. The jitter attenuated clock (ICLK[x] for the RJAT and transmit clock for the
TJAT) are used to read data out of the FIFO.
In E1 mode each jitter attenuator generates the jitter-free 2.048 MHz output
clock by adaptively dividing the 49.152 MHz XCLK signal according to the phase
difference between the jitter attenuated clock and input reference clock.
Fluctuations in the phase of the input data clock are attenuated by the phase-
locked loop within DJAT so that the frequency of the jitter attenuated clock is
equal to the average frequency of the input data clock. Phase fluctuations with a
jitter frequency above 8.8 Hz are attenuated by 6 dB per octave of jitter
frequency. Wandering phase fluctuations with frequencies below 8.8 Hz are
tracked by the jitter attenuated clock. To provide a smooth flow of data out of
DJAT, the jitter attenuated clock is used to read data out of the FIFO.
The TJAT and RJAT have programmable divisors in order to generate the jitter
attenuated clock from the various reference sources. The divisors are set using
the TJAT and RJAT Jitter Attenuator Divider N1 and N2 registers. The following
formula must be met in order to select the values of N1 and N2:
Fin/(N1 + 1) = Fout/(N2 + 1)
where Fin is the input reference clock frequency and Fout is the output jitter
attenuated clock frequency. The values on N1 and N2 can range between 1 and
256. Fin ranges from 8KHz to 2.048MHz in 8KHz increments.
If the FIFO read pointer comes within one bit of the write pointer, DJAT will track
the jitter of the input clock. This permits the phase jitter to pass through
unattenuated, inhibiting the loss of data.
Jitter Characteristics
Each DJAT Block provides excellent jitter tolerance and jitter attenuation while
generating minimal residual jitter. In T1 mode each DJAT can accommodate up
to 28 UIpp of input jitter at jitter frequencies above 6 Hz. For jitter frequencies
below 6 Hz, more correctly called wander, the tolerance increases 20 dB per
decade. In E1 mode each DJAT can accommodate up to 35 UIpp of input jitter at
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
66
PMC [ PMC-SIERRA, INC ]
