STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Generation of the transfer clock within the TEMAP chip is performed by writing to
any counter register location or by writing to the Global PMON Update register.
The holding register addresses are contiguous to facilitate faster polling
operations.
9.4 T1 Alarm Integrator (ALMI)
The T1 Alarm Integration function is provided by the ALMI block. This block
detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or
ESF formats. The alarm detection and integration is compatible with the
specifications defined in ANSI T1.403 and TR-TSY-000191.
The ALMI block declares the presence of Yellow alarm when the Yellow pattern
has been received for 425 ms (± 50 ms); the Yellow alarm is removed when the
Yellow pattern has been absent for 425 ms (± 50 ms). The presence of Red
alarm is declared when an out-of-frame condition has been present for 2.55 sec
(± 40 ms); the Red alarm is removed when the out-of-frame condition has been
absent for 16.6 sec (± 500 ms). The presence of AIS alarm is declared when an
out-of-frame condition and all-ones in the PCM data stream have been present
for 1.5 sec (±100 ms); the AIS alarm is removed when the AIS condition has
been absent for 16.8 sec (±500 ms).
-3
CFA alarm detection algorithms operate in the presence of a 10 bit error rate.
The ALMI also indicates the presence or absence of the Yellow, Red, and AIS
alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively,
allowing an external microprocessor to integrate the alarm conditions via
software with any user-specific algorithms. Alarm indication is provided through
internal register bits.
9.5 Receive and Transmit Digital Jitter Attenuator (RJAT, TJAT)
The Digital Jitter Attenuation function is provided by the DJAT blocks. Each
framer in the TEMAP contains two separate jitter attenuators, one between the
receive demultiplexed or demapped T1 or E1 link and the ingress interface
(RJAT) and the other between the egress interface and the transmit T1 or E1 link
to be multiplexed into DS3 or mapped into SONET (TJAT). Each DJAT block
receives jittered data and stores the stream in a FIFO timed to the associated
receive jittered clock. The jitter attenuated data emerges from the FIFO timed to
the jitter attenuated clock. In the RJAT, the jitter attenuated clock (ICLK[x]) is
referenced to the demultiplexed or demapped tributary receive clock. In the
TJAT, the jitter attenuated transmit tributary clock feeding the M13 multiplexer or
SONET/SDH mapper may be referenced to either CTCLK or the tributary receive
clock.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
65
PMC [ PMC-SIERRA, INC ]
