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PM5365-PI 参数 Datasheet PDF下载

PM5365-PI图片预览
型号: PM5365-PI
PDF下载: 下载PDF文件 查看货源
内容描述: VT / TU映射器和M13多路复用器 [VT/TU MAPPER AND M13 MULTIPLEXER]
分类和应用: 复用器
文件页数/大小: 244 页 / 1139 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM5365 TEMAP  
DATASHEET  
PMC-1991148  
ISSUE 3  
HIGH DENSITY VT/TU MAPPER  
AND M13 MULTIPLEXER  
continue searching for CRC multiframe alignment using the established basic  
frame alignment. In either case, no further adjustments are made to the basic  
frame alignment, and no offline searches for basic frame alignment occur once  
CRC-to-non-CRC interworking is declared: it is assumed that the established  
basic frame alignment at this point is correct.  
AIS Detection  
When an unframed all-ones receive data stream is received, an AIS defect is  
indicated by setting the AISD bit to logic 1 when fewer than three zero bits are  
received in 512 consecutive bits or, optionally, in each of two consecutive periods  
of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512  
consecutive bits or in each of two consecutive periods of 512 bits. Finding frame  
alignment will also cause the AISD bit to be set to logic 0.  
Signaling Frame Alignment  
Once the basic frame alignment has been found, the E1-FRMR searches for  
Channel Associated Signaling (CAS) multiframe alignment using the following  
G.732 compliant algorithm: signaling multiframe alignment is declared when at  
least one non-zero time slot 16 bit is observed to precede a time slot 16  
containing the correct CAS alignment pattern, namely four zeros (“0000”) in the  
first four bit positions of timeslot 16.  
Once signaling multiframe alignment has been found, the E1-FRMR sets the  
OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors  
the signaling multiframe alignment signal, indicating errors occurring in the 4-bit  
pattern, and indicating the debounced value of the Remote Signaling Multiframe  
Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the  
Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being  
-3  
falsely indicated in the presence of a 10 bit error rate.  
The block declares loss of CAS multiframe alignment if two consecutive CAS  
multiframe alignment signals have been received in error, or additionally, if all the  
bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of  
CAS multiframe alignment is also declared if basic frame alignment has been  
lost.  
National Bit Extraction  
The E1-FRMR extracts and assembles the submultiframe-aligned National bit  
codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The  
corresponding register values are updated upon generation of the CRC  
submultiframe interrupt.  
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use  
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